In an image sensor of this general type, the pixels are arranged in rows and columns and each pixel has a read switch which connects the pixel to a vertical line. Horizontal control lines activate the read switches of a row of pixels. These lines are pulsed in sequence to read the light dependent pixel voltages onto the vertical lines. A vertical shift register or decoder is commonly used to generate the read pulse sequence. The voltages on the vertical column lines then pass through a set of elements, one per column, which process the pixel output signals. Typical operations performed by the column elements include storage, amplification, buffering, analog-digital (AD) conversion sampling and comparison.
The column elements add noise in the form of offset voltages to the pixel voltages. The offsets added by each column element vary randomly from column element to column element. Substantially the same offset is applied to each pixel in a given column. This results in vertical shading of the output image, known as “column fixed pattern noise” (column FPN). The main sources of the offsets are mismatches in the charge injection of the sampling switches and amplifier offsets.
Column FPN can be removed by calibrating the image sensor to compensate for the offsets which give rise to column FPN. The sensor is calibrated by applying a known voltage to the inputs of each column element. The resulting column outputs allow the offset for each column to be measured and stored. The measured offsets can subsequently be subtracted from the pixel outputs by analog or digital means. The calibration operation can be performed once per line or once per field. If it is performed once per line, it reduces the time available for pixel conversion. If it is performed once per field, then care must be taken that random thermal noise does not affect the results and that calibration is not influenced by effects not present during normal pixel readout. Such techniques necessarily increase the cost of the sensors.
Solid state image sensors are commonly combined with an analog-to-digital conversion (ADC) function. Two ADC architectures are in common use in CMOS image sensors: per-chip ADC and per-column ADC. In the former, a single high-speed ADC is used to convert all column pixel outputs downstream of the column elements. In the latter, a low speed ADC is incorporated into each column, suitably as part of the column element, so that the analog values of each pixel output voltage of each row are converted in parallel.
FIG. 1 illustrates a conventional per-chip ADC solid state image sensor architecture, comprising a matrix of pixels 10, associated read switches 12, a vertical shift register (decoder) 14, column element circuits 16 and a horizontal shift register (decoder) 18. A 3×3 matrix is shown for the purposes of illustration, wherein the actual matrix would normally be much larger.
An analog readout bus 20 is connected to the single ADC 22. The ADC may be external (off-chip), in which case the analog pixel signals must be driven off-chip, which often requires extra buffering. Alternatively, the ADC may be integrated on-chip with the rest of the sensor, improving speed and power consumption and reducing overall cost. The column elements 16 typically comprise storage capacitors, buffer amplifiers and access switches driven by the horizontal decoder 18. The storage elements hold the pixel voltages ready for conversion by the ADC 22. Buffer amplifiers are required to drive the readout bus 20 and ADC input capacitance. Charge injection of the sampling switches and amplifier offset both contribute to column FPN.
FIG. 2 illustrates a conventional per-column ADC solid state image sensor architecture, again comprising a matrix of pixels 10, read switches 12, a vertical decoder 14, column element circuits 24, incorporating per-column ADC, and a horizontal decoder 18. A digital readout bus 26 provides the sensor output. The column elements 24 include ADC elements, typically comprising sampling capacitors, a reference voltage input (REF), a comparator and digital storage elements. The storage elements hold the pixel voltages for comparison with the reference by the comparator. Charge injection of the sampling switches and amplifier offset again contribute to column FPN.